The present invention relates to a power supply structure and a power supply design method of a semiconductor integrated circuit for specifying a part where electromigration (EM) may occur and for reducing the incidence of EM in a layout process of the semiconductor integrated circuit having a multilayer interconnection configuration.
Conventionally, in a power supply design in a layout process of a semiconductor integrated circuit, a ring power supply may be formed of a pair of power supply VDD and ground VSS positioned such that the pair of power supply VDD and ground VSS are surrounded by IO terminals. In this case, in order to simplify a wire arrangement process, one layer is used in a vertical direction and another layer is used in a horizontal direction.
FIG. 1 shows ring power supplies and a power supply wiring arrangement between an IO and the ring power supplies of a conventional semiconductor integrated circuit. Referring to FIG. 1, ring power supplies 3 and 4 are positioned such that the ring power supplies 3 and 4 are surrounded by an IO terminal region 1. The vertical direction ring power supplies 3 and the horizontal direction ring power supplies 4 are connected each other by vias (contacts) 5. Here, the inner ring is designated as VDD and the outer ring is designated as VSS. However, VDD and VSS may be reversed. In order to avoid a short circuit, a layer of a power supply wire 7 connecting the vertical direction ring power supply 3 with a power supply (VDD) terminal 2 is formed of a layer different from a layer of the vertical direction ring power supply 3. Likewise, in order to avoid a short circuit, a layer of a power supply wire 6 connecting the horizontal direction ring power supply 4 with another power supply (VDD) terminal is formed of a layer different from a layer of the horizontal direction ring power supply 4.
In FIG. 1, the layer of the vertical direction ring power supply is designated, for example, as Mx, and the layer of the horizontal direction ring power supply is designated, for example, as Mx−1. In this case, in order to avoid a short circuit, the power supply wire 7 connected between the IO and the vertical direction ring power supply (Mx) is the layer designated as Mx−1, and the power supply wire 6 connected between the IO and the horizontal direction ring power supply (Mx−1) is the layer designated as Mx.
As to the current threshold value of each layer, an upper layer generally has a current threshold value higher than that of a lower layer (Mx>Mx−1). Therefore, the power supply wire through which the greatest magnitude of current flows between the IO and the ring power supply must be the upper layer. Otherwise, a current exceeding the current threshold value flows through the power supply wire. Consequently, EM may occur which causes breaking of wire (In FIG. 1, a critical part where breaking of wire may occur is indicated by reference number 7).
In order to cope with this problem, following measures against EM have been taken: broadening the width of a wire between the IO and the ring power supply, and increasing the number of vias.
Meanwhile, the maximum wire width of each layer reduces as process miniaturization advances. Therefore, a plurality of thin power supplies are generally arranged in mesh form. Considering the worker-hour, it has been common that a mesh power supply and a strap power supply have a constant pitch (see Japanese Laid-Open Patent Publication No. 7-283378).
In this case, an arrangement position of a macro, a power supply arrangement inside the macro or the like causes a part to where a sufficient number of contacts can not be provided. Also in such case where the sufficient number of contacts can not be provided, the current threshold value of the via is exceeded. Consequently, the possibility of the EM incidence increases.
To cope with the problem, it has been proposed that the via is provided with a reservoir as a measure against EM (see Japanese Laid-Open Patent Publication No. 2003-318260).
In recent years, semiconductor process miniaturization has been rapidly increasing the number of circuits (functions) integrated on a chip. However, decrease in the number of terminals is slower than increase in circuit integrity resulting from the process miniaturization. Therefore, the number of cases is increasing that the number of terminals determines the chip size.
In many cases, the number of power supply terminals is reduced in order to reduce the total number of terminals. When the number of power supply terminals is reduced, problems arise such as voltage drop and EM.